AMD has joined forces with the Compute Express Link (CXL) Consortium, a group dedicated to creating open standards for high-speed interconnects between processors, systems, devices, graphics accelerators, and memory buffers.
CXL was actually originally formed by Intel and eight other founding members, announcing the CXL Specification 1.0 back in March of this year. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, and Microsoft. Each of them is dedicated to forming a new open industry standard for high-speed interconnects between devices such as CPU-to-CPU, CPU-to-GPU, and other system devices.
“Designed to address the increasing demands of high-performance computational workloads, CXL targets heterogeneous processing and memory systems across a range of high-performance computing applications by enabling coherency and memory semantics between processors and systems,” wrote AMD CTO Mark Papermaster in an announcement.
“This is increasingly important as processing data in Artificial Intelligence and Machine Learning requires a diverse mix of scalar, vector, matrix and spatial architectures across a range of accelerator options.”
CLX relies heavily on the upcoming PCIe 5.0 standard, building upon this to open the door to faster computation, deep learning, AI, cloud computing, The interconnect will connect CPUs, accelerators, and memory with lower latency and higher throughput than is currently possible. The essential benefit here is reducing the performance overhead when devices cross-communicate.
There are a number of competing standards in this area, including CCIX, Gen-Z, and CXL, although unifying around a universal open standard would appear to be the sensible choice. All the big boys have collaborated around CXL so it’s on track to become the dominant standard.